/*
 * Shared LARK WiFi Header
 *
 * Register map, hardware-specific definitions
 *
 * Copyright 2014, CJTian <cjtian@actions-semi.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; see the file COPYING.  If not, see
 * http://www.gnu.org/licenses/.
 *
 * This file incorporates work covered by the following copyright and
 * permission notice:
 *    Copyright (c) 2007-2014 Actions Semi Conductor, Inc.
 *
 *    Permission to use, copy, modify, and/or distribute this software for any
 *    purpose with or without fee is hereby granted, provided that the above
 *    copyright notice and this permission notice appear in all copies.
 *
 *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef __LARK_SHARED_HW_H
#define __LARK_SHARED_HW_H

#define PA_BASE             0xb0200000
#define CE_BASE             0xb0210000
#define UART0_BASE			0xB0160000

/*****************************************************************************/
/* Protocol Accelerator Register Addresses                                   */
/*****************************************************************************/

/*****************************************************************************/
/* General Registers                                                         */
/*****************************************************************************/

#define MAC_PA_VER                   (PA_BASE + 0x0000)
#define MAC_PA_CON                   (PA_BASE + 0x0004)
#define MAC_PA_STAT                  (PA_BASE + 0x0008)
#define MAC_ADDR_HI                  (PA_BASE + 0x000C)
#define MAC_ADDR_LO                  (PA_BASE + 0x0010)
#define MAC_BSSID_HI                 (PA_BASE + 0x0014)
#define MAC_BSSID_LO                 (PA_BASE + 0x0018)
#define MAC_PRBS_SEED_VAL            (PA_BASE + 0x001C)
#define MAC_PA_DMA_BURST_SIZE        (PA_BASE + 0x0020)
#define MAC_TX_RX_COMPLETE_CNT       (PA_BASE + 0x0024)
#define MAC_PRBS_READ_CTRL           (PA_BASE + 0x0028)
#define MAC_NULL_FRAME_RATE          (PA_BASE + 0x002C)
#define MAC_NULL_FRAME_PHY_TX_MODE   (PA_BASE + 0x0030)
#define MAC_TEST_MODE                (PA_BASE + 0x0034)
#define MAC_HW_ID                    (PA_BASE + 0x0038)
#define MAC_RESET_CTRL               (PA_BASE + 0x003C)
#define MAC_TX_ABORT_FRM_DUR_TIMEOUT (PA_BASE + 0x0040)
#define MAC_TX_ABORT_FRM_RATE        (PA_BASE + 0x0044)
#define MAC_TX_ABORT_FRM_PHY_TX_MODE (PA_BASE + 0x0048)
#define MAC_EXTENDED_PA_CON          (PA_BASE + 0x004C)

/*****************************************************************************/
/* Reception Registers                                                       */
/*****************************************************************************/

#define MAC_RX_FRAME_FILTER          (PA_BASE + 0x0080)
#define MAC_FRAME_CON                (PA_BASE + 0x0084)
#define MAC_RX_BUFF_ADDR             (PA_BASE + 0x0088)
#define MAC_FCS_FAIL_COUNT           (PA_BASE + 0x008C)
#define MAC_RXMAXLEN_FILT            (PA_BASE + 0x0090)
#define MAC_DUP_DET_COUNT            (PA_BASE + 0x0094)
#define MAC_RX_END_COUNT             (PA_BASE + 0x0098)
#define MAC_RX_ERROR_END_COUNT       (PA_BASE + 0x009C)
#define MAC_AMPDU_RXD_COUNT          (PA_BASE + 0x00A0)
#define MAC_RX_MPDUS_IN_AMPDU_COUNT  (PA_BASE + 0x00A4)
#define MAC_RX_BYTES_IN_AMPDU_COUNT  (PA_BASE + 0x00A8)
#define MAC_AMPDU_DLMT_ERROR_COUNT   (PA_BASE + 0x00AC)
#define MAC_RX_LIFETIME_LIMIT        (PA_BASE + 0x00B0)
#define MAC_HIP_RX_BUFF_ADDR         (PA_BASE + 0x00B4)
#define MAC_HIP_RXQ_CON              (PA_BASE + 0x00B8)
#define MAC_SUB_MSDU_GAP             (PA_BASE + 0x00BC)
#define MAC_MAX_RX_BUFFER_LEN        (PA_BASE + 0x00C0)

/*****************************************************************************/
/* EDCA Registers                                                            */
/*****************************************************************************/

#define MAC_AIFSN                     (PA_BASE + 0x0100)
#define MAC_CW_MIN_MAX_AC_BK          (PA_BASE + 0x0104)
#define MAC_CW_MIN_MAX_AC_BE          (PA_BASE + 0x0108)
#define MAC_CW_MIN_MAX_AC_VI          (PA_BASE + 0x010C)
#define MAC_CW_MIN_MAX_AC_VO          (PA_BASE + 0x0110)
#define MAC_EDCA_TXOP_LIMIT_AC_BKBE   (PA_BASE + 0x0114)
#define MAC_EDCA_TXOP_LIMIT_AC_VIVO   (PA_BASE + 0x0118)
#define MAC_EDCA_PRI_BK_Q_PTR         (PA_BASE + 0x011C)
#define MAC_EDCA_PRI_BK_RETRY_CTR     (PA_BASE + 0x0120)
#define MAC_EDCA_PRI_BE_Q_PTR         (PA_BASE + 0x0124)
#define MAC_EDCA_PRI_BE_RETRY_CTR     (PA_BASE + 0x0128)
#define MAC_EDCA_PRI_VI_Q_PTR         (PA_BASE + 0x012C)
#define MAC_EDCA_PRI_VI_RETRY_CTR     (PA_BASE + 0x0130)
#define MAC_EDCA_PRI_VO_Q_PTR         (PA_BASE + 0x0134)
#define MAC_EDCA_PRI_VO_RETRY_CTR     (PA_BASE + 0x0138)
#define MAC_EDCA_PRI_HP_Q_PTR         (PA_BASE + 0x013C)
#define MAC_TX_MSDU_LIFETIME          (PA_BASE + 0x0140)
#define MAC_EDCA_BK_BE_LIFETIME       (PA_BASE + 0x0144)
#define MAC_EDCA_VI_VO_LIFETIME       (PA_BASE + 0x0148)
#define MAC_AMPDU_RETRY_LIMIT         (PA_BASE + 0x0150)

/*****************************************************************************/
/* HCCA STA Registers                                                        */
/*****************************************************************************/

#define MAC_HC_STA_PRI0_Q_PTR        (PA_BASE + 0x0180)
#define MAC_HC_STA_PRI1_Q_PTR        (PA_BASE + 0x0184)
#define MAC_HC_STA_PRI2_Q_PTR        (PA_BASE + 0x0188)
#define MAC_HC_STA_PRI3_Q_PTR        (PA_BASE + 0x018C)
#define MAC_HC_STA_PRI4_Q_PTR        (PA_BASE + 0x0190)
#define MAC_HC_STA_PRI5_Q_PTR        (PA_BASE + 0x0194)
#define MAC_HC_STA_PRI6_Q_PTR        (PA_BASE + 0x0198)
#define MAC_HC_STA_PRI7_Q_PTR        (PA_BASE + 0x019C)

/*****************************************************************************/
/* TSF Registers                                                             */
/*****************************************************************************/

#define MAC_TSF_CON                  (PA_BASE + 0x0200)
#define MAC_TSF_TIMER_HI             (PA_BASE + 0x0204)
#define MAC_TSF_TIMER_LO             (PA_BASE + 0x0208)
#define MAC_BEACON_PERIOD            (PA_BASE + 0x020C)
#define MAC_DTIM_PERIOD              (PA_BASE + 0x0210)
#define MAC_BEACON_POINTER           (PA_BASE + 0x0214)
#define MAC_BEACON_TX_PARAMS         (PA_BASE + 0x0218)
#define MAC_DTIM_COUNT               (PA_BASE + 0x021C)
#define MAC_AP_DTIM_COUNT            (PA_BASE + 0x0220)
#define MAC_BEACON_PHY_TX_MODE       (PA_BASE + 0x0224)
#define MAC_TBTT_TIMER               (PA_BASE + 0x0228)

/*****************************************************************************/
/* Protection And SIFS Response Registers                                    */
/*****************************************************************************/

#define MAC_PROT_CON                 (PA_BASE + 0x0280)
#define MAC_RTS_THRESH               (PA_BASE + 0x0284)
#define MAC_PROT_RATE                (PA_BASE + 0x0288)
#define MAC_TXOP_HOLDER_ADDR_HI      (PA_BASE + 0x028C)
#define MAC_TXOP_HOLDER_ADDR_LO      (PA_BASE + 0x0290)
#define MAC_FRAG_THRESH              (PA_BASE + 0x029C)
#define MAC_PROT_TX_MODE             (PA_BASE + 0x02A0)
#define MAC_HT_CTRL                  (PA_BASE + 0x02A4)
#define MAC_AMPDU_LUT_CTRL           (PA_BASE + 0x02A8)
#define MAC_AMPDU_TXD_COUNT          (PA_BASE + 0x02AC)
#define MAC_TX_MPDUS_IN_AMPDU_COUNT  (PA_BASE + 0x02B0)
#define MAC_TX_BYTES_IN_AMPDU_COUNT  (PA_BASE + 0x02B4)

#define TX_NUM_20MHZ_TXOP               (PA_BASE + 0x02BC)
#define TX_NUM_40MHZ_TXOP               (PA_BASE + 0x02C0)
#define TX_NUM_20MHZ_MPDU_IN_40MHZ_TXOP (PA_BASE + 0x02C4)
#define TX_NUM_PROMOTED_MPDU            (PA_BASE + 0x02C8)
#define TX_NUM_MPDU_DEMOTED             (PA_BASE + 0x02CC)
#define TX_NUM_PROMOTED_PROT            (PA_BASE + 0x02D0)
#define TX_NUM_PROT_DUE_TO_FC           (PA_BASE + 0x02D4)
#define TX_NUM_TXOP_ABORT_ON_SEC_BUSY   (PA_BASE + 0x02D8)

/*****************************************************************************/
/* Channel Access Timer Management Registers                                 */
/*****************************************************************************/

#define MAC_SLOT_TIME                (PA_BASE + 0x0300)
#define MAC_SIFS_TIME                (PA_BASE + 0x0304)
#define MAC_EIFS_TIME                (PA_BASE + 0x0308)
#define MAC_PPDU_MAX_TIME            (PA_BASE + 0x030C)
#define MAC_SEC_CHAN_SLOT_COUNT      (PA_BASE + 0x0310)
#define MAC_SIFS_TIME2               (PA_BASE + 0x0314)
#define MAC_RIFS_TIME_CONTROL_REG    (PA_BASE + 0x0318)

/*****************************************************************************/
/* Retry Registers                                                           */
/*****************************************************************************/

#define MAC_LONG_RETRY_LIMIT         (PA_BASE + 0x0380)
#define MAC_SHORT_RETRY_LIMIT        (PA_BASE + 0x0384)

/*****************************************************************************/
/* Sequence Number and Duplicate Detection Registers                         */
/*****************************************************************************/

#define MAC_SEQ_NUM_CON              (PA_BASE + 0x0400)
#define MAC_STA_ADDR_HI              (PA_BASE + 0x0404)
#define MAC_STA_ADDR_LO              (PA_BASE + 0x0408)
#define MAC_TX_SEQ_NUM               (PA_BASE + 0x040C)

/*****************************************************************************/
/* PCF Registers                                                             */
/*****************************************************************************/

#define MAC_PCF_CON                  (PA_BASE + 0x0480)
#define MAC_CFP_MAX_DUR              (PA_BASE + 0x0484)
#define MAC_CFP_INTERVAL             (PA_BASE + 0x0488)
#define MAC_CFP_PARAM_SET_BYTE_NUM   (PA_BASE + 0x048C)
#define MAC_MEDIUM_OCCUPANCY         (PA_BASE + 0x0490)
#define MAC_PCF_Q_PTR                (PA_BASE + 0x0494)
#define MAC_CFP_COUNT                (PA_BASE + 0x0498)
#define MAC_UNUSED_CFP_DUR           (PA_BASE + 0x049C)

/*****************************************************************************/
/* Power Management Registers                                                */
/*****************************************************************************/

#define MAC_PM_CON                   (PA_BASE + 0x0500)
#define MAC_ATIM_WINDOW              (PA_BASE + 0x0504)
#define MAC_LISTEN_INTERVAL          (PA_BASE + 0x0508)
#define MAC_OFFSET_INTERVAL          (PA_BASE + 0x050C)
#define MAC_S_APSD_SSP               (PA_BASE + 0x0510)
#define MAC_S_APSD_SI                (PA_BASE + 0x0514)
#define MAC_SMPS_CONTROL             (PA_BASE + 0x0518)
#define MAC_LISTEN_INTERVAL_TIMER    (PA_BASE + 0x051C)
/*****************************************************************************/
/* Interrupt Registers                                                       */
/*****************************************************************************/

#define MAC_INT_STAT                 (PA_BASE + 0x0580)
#define MAC_INT_MASK                 (PA_BASE + 0x0584)
#define MAC_TX_FRAME_POINTER         (PA_BASE + 0x0588)
#define MAC_RX_FRAME_POINTER         (PA_BASE + 0x058C)
#define MAC_ERROR_CODE               (PA_BASE + 0x0590)
#define MAC_TX_MPDU_COUNT            (PA_BASE + 0x0594)
#define MAC_RX_MPDU_COUNT            (PA_BASE + 0x0598)
#define MAC_HIP_RX_FRAME_POINTER     (PA_BASE + 0x059C)
#define MAC_DEAUTH_REASON_CODE       (PA_BASE + 0x05A0)
#define MAC_ERROR_STAT               (PA_BASE + 0x05A4)
#define MAC_ERROR_MASK               (PA_BASE + 0x05A8)

/*****************************************************************************/
/* PHY Interface and Parameters Register                                     */
/*****************************************************************************/

#define MAC_PHY_REG_ACCESS_CON       (PA_BASE + 0x0638)
#define MAC_PHY_REG_RW_DATA          (PA_BASE + 0x063C)
#define MAC_PHY_RF_REG_BASE_ADDR     (PA_BASE + 0x0624)
#define MAC_TXPLCP_DELAY             (PA_BASE + 0x0628)
#define MAC_RXPLCP_DELAY             (PA_BASE + 0x062C)
#define MAC_RXTXTURNAROUND_TIME      (PA_BASE + 0x0630)
#define MAC_PHY_TIMEOUT_ADJUST       (PA_BASE + 0x0634)
#define MAC_PHY_SERVICE_FIELD        (PA_BASE + 0x0640)
#define MAC_PHY_TX_PWR_SET_REG       (PA_BASE + 0x0644)
#define MAC_PHY_CCA_DELAY            (PA_BASE + 0x0648)
#define MAC_TXPLCP_ADJUST_VAL        (PA_BASE + 0x064C)
#define MAC_RXPLCP_DELAY2            (PA_BASE + 0x0650)
#define MAC_RXSTART_DELAY_REG        (PA_BASE + 0x0654)
#define MAC_ANTENNA_SET              (PA_BASE + 0x0658)

/*****************************************************************************/
/* Block Ack register address                                                */
/*****************************************************************************/

#define MAC_BA_CTRL                 (PA_BASE + 0x0698)
#define MAC_BA_PEER_STA_ADDR_MSB    (PA_BASE + 0x069C)
#define MAC_BA_PEER_STA_ADDR_LSB    (PA_BASE + 0x06A0)
#define MAC_BA_PARAMS               (PA_BASE + 0x06A4)
#define MAC_BA_CBMAP_MSW            (PA_BASE + 0x06A8)
#define MAC_BA_CBMAP_LSW            (PA_BASE + 0x06AC)

/*****************************************************************************/
/* HCCA AP Registers                                                         */
/*****************************************************************************/

#define MAC_SCHEDULE_LINK_ADDR      (PA_BASE + 0x0700)
#define MAC_CAP_START_TIME          (PA_BASE + 0x0704)

/*****************************************************************************/
/* Queue pointer addresses                                                   */
/*****************************************************************************/

#define MAC_EDCA_PRI_BK_Q_PTR         (PA_BASE + 0x011C)
#define MAC_EDCA_PRI_BE_Q_PTR         (PA_BASE + 0x0124)
#define MAC_EDCA_PRI_VI_Q_PTR         (PA_BASE + 0x012C)
#define MAC_EDCA_PRI_VO_Q_PTR         (PA_BASE + 0x0134)
#define MAC_EDCA_PRI_HP_Q_PTR         (PA_BASE + 0x013C)
#define MAC_EDCA_PRI_CF_Q_PTR         (PA_BASE + 0x0494)
#define MAC_HC_STA_PRI0_Q_PTR         (PA_BASE + 0x0180)
#define MAC_HC_STA_PRI1_Q_PTR         (PA_BASE + 0x0184)
#define MAC_HC_STA_PRI2_Q_PTR         (PA_BASE + 0x0188)
#define MAC_HC_STA_PRI3_Q_PTR         (PA_BASE + 0x018C)
#define MAC_HC_STA_PRI4_Q_PTR         (PA_BASE + 0x0190)
#define MAC_HC_STA_PRI5_Q_PTR         (PA_BASE + 0x0194)
#define MAC_HC_STA_PRI6_Q_PTR         (PA_BASE + 0x0198)
#define MAC_HC_STA_PRI7_Q_PTR         (PA_BASE + 0x019C)

/*****************************************************************************/
/* CE Register Addresses                                                     */
/*****************************************************************************/

#define MAC_CE_KEY_FIRST             (CE_BASE + 0x0000)
#define MAC_CE_KEY_SECOND            (CE_BASE + 0x0004)
#define MAC_CE_KEY_THIRD             (CE_BASE + 0x0008)
#define MAC_CE_KEY_FOURTH            (CE_BASE + 0x000C)
#define MAC_CE_MAC_ADDR_MSB          (CE_BASE + 0x0010)
#define MAC_CE_MAC_ADDR_LSB          (CE_BASE + 0x0014)
#define MAC_CE_STA_ADDR_MSB          (CE_BASE + 0x0018)
#define MAC_CE_STA_ADDR_LSB          (CE_BASE + 0x001C)
#define MAC_CE_LUT_OPERN             (CE_BASE + 0x0020)
#define MAC_CE_LUT_STATUS            (CE_BASE + 0x0024)
#define MAC_CE_GTK_PN_MSB            (CE_BASE + 0x0028)
#define MAC_CE_GTK_PN_LSB            (CE_BASE + 0x002C)
#define MAC_CE_CONFIG                (CE_BASE + 0x0030)
#define MAC_CE_RX_GRP_CIPHER_TYPE    (CE_BASE + 0x0034)
#define MAC_CE_CONTROL               (CE_BASE + 0x0038)
#define MAC_CE_TKIP_MIC_KEY_Q1       (CE_BASE + 0x003C)
#define MAC_CE_TKIP_MIC_KEY_Q2       (CE_BASE + 0x0040)
#define MAC_CE_TKIP_MIC_KEY_Q3       (CE_BASE + 0x0044)
#define MAC_CE_TKIP_MIC_KEY_Q4       (CE_BASE + 0x0048)
#define MAC_CE_TKIP_REPLAY_FAIL_CNT  (CE_BASE + 0x004C)
#define MAC_CE_CCMP_REPLAY_FAIL_CNT  (CE_BASE + 0x0050)
#define MAC_CE_RX_BC_PN_MSB          (CE_BASE + 0x0054)
#define MAC_CE_RX_BC_PN_LSB          (CE_BASE + 0x0058)

/*****************************************************************************/
/* Miscellaneous Register Addresses (Arbiter, DMA, Host select etc)          */
/*****************************************************************************/

/*****************************************************************************/
/* Reset Control                                                             */
/*****************************************************************************/
#define MACPHYRESCNRTL               (PA_BASE + 0x40004))

/*****************************************************************************/
/* P2P Registers                                                             */
/*****************************************************************************/

#define  P2P_CNTRL_REG            (PA_BASE + 0x0800)
#define  P2P_NOA_CNT_STATUS_REG   (PA_BASE + 0x0804)
#define  P2P_NOA1_DURATION_REG    (PA_BASE + 0x0808)
#define  P2P_NOA1_INTERVAL_REG    (PA_BASE + 0x080C)
#define  P2P_NOA1_START_TIME_REG  (PA_BASE + 0x0810)
#define  P2P_NOA2_DURATION_REG    (PA_BASE + 0x0814)
#define  P2P_NOA2_INTERVAL_REG    (PA_BASE + 0x0818)
#define  P2P_NOA2_START_TIME_REG  (PA_BASE + 0x081C)
#define  P2P_EOA_OFFSET           (PA_BASE + 0x0820)
#define  P2P_STATUS_REG           (PA_BASE + 0x0824)



/*****************************************************************************/
/* MISC Register Addresses                                                     */
/*****************************************************************************/
#define  UART0_CTL					(UART0_BASE+0x0000)
#define  UART0_RXDAT				(UART0_BASE+0x0004)
#define  UART0_TXDAT				(UART0_BASE+0x0008)
#define  UART0_STAT					(UART0_BASE+0x000c)




#endif /* __LARK_SHARED_HW_H */
